Towards Chip-Scale Plasmonic Interconnects

In the multi and many core era, communication is crucial to the system performance. Therefore, network-on-chip (NoC) approaches were proposed to regularize the design of on-chip communication. Nanophotonic interconnects have been proposed in the recent few years as a replacement of global metal interconnect because of their almost distance-independent power consumption and low-latency and high bandwidth. However, photonic components have their limitations: diffraction-limited sizes, temperature dependence and cross-talk and bend losses. First, nanophotonic components are governed by the diffraction limit which dictates that light cannot be confined in a space smaller than λ/2n where λ is the free space wavelength and n is the refractive index of the material. This means that the size of waveguides and modulators and ring filters are in the micrometer scale because of usage of C-band around 1550 nm wavelength. This size mismatch between micrometer-scale photonic components and nanometer-scale electronic ones limits the integration viability of both technologies on the same chip using the same process. These relatively bigger size components have higher capacitance which requires more power consumption to drive and limits the speed at which they can operate. For example, a photonic link is expected to have around 158 fJ/bit electric and electro-optical components energy consumption per bit [1] which is clearly over the estimated viability requirement of 10 fJ/bit per device [7]. Second, photonic components are temperature-dependent which is exploited in the micro-ring modulators that their resonance range is adjusted using heating. This heating requirement is estimated to consume around 100 fJ/bit [1]. These two major power consumption components limit the minimum distance at which nanophotonic waveguides can be more power efficient than electrical signaling, even excluding offlaser generator power consumption. Third, because of low confinement, bend losses and cross-talk are a problem for nanophotonic devices. The minimum pitch of a Si waveguide is 5.5 μm. This paper introduces a new technology for interconnects, plasmonics, that provides an alternative to a purely photonic interconnect for many-core processors.